
Preliminary Technical Data
ADL5356
REV. PrE | Page 9 of 10
Components
Function
Default Conditions
C1, C4, C5, C8, C10, C12,
C13, C15, C18, C21, C22,
C23, C24, C25, C26
Power Supply Decoupling. Nominal supply decoupling consists a
0.01 μF capacitor to ground in parallel with 10pF capacitors to
ground positioned as close to the device as possible.
C10 = 4.7 μF (size 3216)
C1, C8, C12, C21 = 150pF (size 0402)
C4, C5, C22, C23, C24, C25, C26 = 10pF
(size 0402)
C13, C15, C18 = 0.1 μ (size 0402)
Z1-Z4, C2, C3, C6, C7, C9,
C22
RF Main and Diversity Input Interface. Main and Diversity input
channels are ac-coupled through C9 and C22. Z1-Z4 provides
additional component placement for external matching/filter
networks. C2, C3, C6, and C7 provide bypassing for the center taps
of the main and diversity on-chip input baluns.
C2, C7 = 10pF (size 0402)
C3, C6 = 0.01 μF (size 0402)
C9, C22 = 22pF (size 0402)
Z1-Z4 = open (size 0402)
T1, T2, C17, C19, C20, C27,
C28, C29, C30, C31, C32,
C33, L1, L2, L4, L5, R3, R6,
R9, R10
IF Main and Diversity Output Interface. The open collector IF output
interfaces are biased through pull-up choke inductors L1, L2, L4, and
L5, with R3 and R6 available for additional supply bypassing. T1 and
T2 are 4:1 impedance transformers used to provide a single ended IF
output interface, with C27 and C28 providing center-tap bypassing.
C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled
output interface. R9 and R10 should be removed for balanced
output operation.
C17, C19, C20, C29-C33 = 0.001 μF (size
0402)
C27, C28 = 150pF (size 0402)
T1, T2 = TC4-1T+ (MiniCircuits)
L1, L2, L4, L5 = 330 nH (size 0805)
R3, R6, R9, R10 = 0 Ω (size 0402)
C14, C16, R15, LOSEL
LO Interface. C14 and C16 provide ac-coupling for the LOI1 and LOI2
local oscillator inputs. LOSEL selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is
enabled when the LOSEL jumper is removed. Jumper can be
removed to allow LOSEL interface to be excercised using external
logic generator.
C14, C16 = 10pF (size 0402)
R15 = 10k
Ω (size 0402)
LOSEL = 2-pin shunt
R19, PWDN
PWDN Interface. When the PWDN 2-pin shunt is inserted the
ADL5356 is powered down. When open R19 pulls the PWDN logic
low and enables the device. Jumper can be removed to allow PWDN
interface to be excercised using external logic generator. It is
permissible to ground the pwrdn pin for nominal operation.
R19 = 10k
Ω (size 0402)
PWDN = 2-pin shunt
R1, R2, R4, R5,L3, L6, R7,
R8, R11, R12, R13, R14,
R16, R17, C34
Bias Control. R16 and R17 form a voltage divider to provide a 3V for
logic control, bypassed to ground through C34. R7, R8, R11, R12,
R13, and R14 provide resistor programmability of VGS0, VGS1 and
VGS2. Typically these nodes can be hard-wired for nominal
operation. It is permissible to ground these pins for nominal
operation. R2 and R5 set the bias point for the internal LO buffers. R1
and R4 set the bias point for the internal IF amplifiers. L3 and L6 are
external inductors used to improve isolation and common mode
rejection.
R1, R4 = 1.54k
Ω (size 0402)
R2, R5 = 390
Ω (size 0402)
L3, L6 = 0
Ω (size 0603)
R12, R13, R14 = open (size 0402)
R7, R8, R11 = 0
Ω (size 0402)
R16 = 10k
Ω (size 0402)
R17 = 15k
Ω (size 0402)
C34 = 1nF (size 0402)