參數(shù)資料
型號(hào)： DS17485SN-5+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 6/31頁(yè)
文件大?。?/td> 0K
描述： IC RTC 5V 4K NV RAM 24-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 31
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出
存儲(chǔ)容量： 4KB
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 4.5 V ~ 5.5 V
電壓 - 電源，電池： 2.5 V ~ 3.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
Bit 7: Update In Progress (UIP). This bit is a status
flag that can be monitored. When the UIP bit is 1, the
update transfer will soon occur. When UIP is 0, the
update transfer does not occur for at least 244s. The
time, calendar, and alarm information in RAM is fully
available for access when the UIP bit is 0. The UIP bit is
read-only. Writing the SET bit in Register B to 1 inhibits
any update transfer and clears the UIP status bit.
Bits 6, 5, and 4: DV2, DV1, and DV0. These bits are
used to turn the oscillator on or off and to reset the
countdown chain. A pattern of 01X is the only combina-
tion of bits that turns the oscillator on and allows the RTC
to keep time. A pattern of 11X enables the oscillator but
holds the countdown chain in reset. The next update
occurs at 500ms after a pattern of 01X is written to DV0,
DV1, and DV2. DV0 is used to select bank 0 or bank 1 as
defined in Table 5. When DV0 is set to 0, bank 0 is
selected. When DV0 is set to 1, bank 1 is selected.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
14
____________________________________________________________________
Table 3B. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1)
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds regis-
ter, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
00h
0
Seconds
00–3B
01h
0
Seconds
Seconds Alarm
00–3B
02h
0
Minutes
00–3B
03h
0
Minutes
Minutes Alarm
00–3B
AM/PM
0
Hours
04h
0
00
Hours
1–0C +AM/PM
00–17
AM/PM
0
Hours
05h
0
00
Hours
Hours Alarm
1–0C +AM/PM
00–17
06h
0
Day
01–07
07h
0
Date
01–1F
08h
0
Month
01–0C
09h
0
Year
00–63
0Ah
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
Control
—
0Bh
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Control
—
0Ch
IRQF
PF
AF
UF
0
Control
—
0Dh
VRT
0
Control
—
Bank 1, 48h
10 Century
Century
00–63
Bank 1, 49h
10 Date
Date
Date Alarm
01–1F
Control Registers
The four control registers (A, B, C, and D) reside in
both bank 0 and bank 1. These registers are accessi-
ble at all times, even during the update cycle.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
Register A (0Ah)
MSB
LSB
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