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參數(shù)資料
| 型號(hào)： | SC16C650BIB48,128 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SOT313-2 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935274391128 SC16C650BIB48-F SC16C650BIB48-F-ND |
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SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
22 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch and enhanced feature register enabled
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition exists
until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5
LCR[5]
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.
Programs the parity conditions (see Table 16).
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the
transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the
transmit and receive data
4
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]
selects the even or odd parity format.
logic 0 = odd parity is generated by forcing an odd number of logic 1s in the
transmitted data. The receiver must be programmed to check the same
format (normal default condition).
logic 1 = even parity is generated by forcing an even number of logic 1s in
the transmitted data. The receiver must be programmed to check the same
format.
3
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver checks
the data and parity for transmission errors
2
LCR[2]
Stop bits. The length of stop bit is specied by this bit in conjunction with the
programmed word length (see Table 17).
logic 0 or cleared = default condition
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be transmitted
or received (see Table 18).
logic 0 or cleared = default condition
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