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參數(shù)資料
| 型號： | 70T3399S133BCGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 327K |
| 代理商： | 70T3399S133BCGI8 |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
19
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
Timing Waveform of Counter Repeat(2)
NOTES:
1.
CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when
ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during
REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7.
CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS
An
CLK
DATAIN
Dn
Dn + 1
Dn + 2
ADS
CNTEN
tCH2
tCL2
tCYC2
5652 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
tSA
tHA
tSAD tHAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
tSCN tHC
N
,
ADDRESS
An
D0
tCH2
tCL2
tCYC2
QLAST
QLAST+1
LAST
ADS LOAD
CLK
DATAIN
R/W
REPEAT
5652 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
tSRPT tHRPT
tSD
tHD
tSW tHW
EXECUTE
REPEAT
WRITE
LAST
ADS
ADDRESS
READ
LAST
ADS
ADDRESS
READ
LAST
ADS
ADDRESS + 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATAOUT
tSA tHA
LAST
ADS +1
An
An + 1
(4)
(5)
(6)
Ax
tSAD tHAD
tSCN tHCN
,
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 70T3399S133BCI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Rail/Tube |
| 70T3399S133BCI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Tape and Reel |
| 70T3399S133BF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
| 70T3399S133BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Tape and Reel |
| 70T3399S133BFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
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