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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD7276AUJZ-REEL7
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/29闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 12BIT 3MSPS 6TSOT
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 3,000
浣嶆暩(sh霉)锛� 12
閲囨ǎ鐜囷紙姣忕锛夛細 3M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI?
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 1
鍔熺巼鑰楁暎锛堟渶澶э級锛� 19.8mW
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宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� SOT-23-6 绱�(x矛)鍨�锛孴SOT-23-6
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 TSOT-23-6
鍖呰锛� 甯跺嵎 (TR)
杓稿叆鏁�(sh霉)鐩拰椤�(l猫i)鍨嬶細 1 鍊�(g猫)鍠锛屽柈妤�
AD7276/AD7277/AD7278
Rev. C | Page 10 of 28
TIMING EXAMPLES
For the AD7276, if CS is brought high during the 14
th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If CS is brought high during the 16
th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the
throughput is 3 MSPS. This produces a cycle time of t2 +
12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and
tACQ = 67 ns.
This satisfies the requirement of 60 ns for tACQ. Figure 6 also
shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where
t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying
the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and
tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 +
tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
04
90
3-
0
05
1
2
34
5
1314
15
16
SCLK
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
2 TRAILING
ZEROS
B
CS
t3
tCONVERT
t2
ZERO
Z
DB11
DB10
DB9
DB1
DB0
ZERO
t6
t5
t8
t1
tQUIET
1/THROUGHPUT
t4
t7
Figure 5. AD7276 Serial Interface Timing Diagram
04
90
3-
0
34
tQUIET
tCONVERT
1/THROUGHPUT
CS
15
13
t4
234
t5
t3
t2
t6
t7
t9
14
B
t1
SCLK
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
ZZERO
DB11
DB10
DB9
DB1
DB0
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
04
90
3-
00
6
123
4
5
13
12
14
15
16
SCLK
B
CS
tCONVERT
t2
t8
t1
tQUIET
1/THROUGHPUT
12.5(1/fSCLK)
tACQUISITION
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle
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